1. Field of the Invention
The present invention relates to a synchronizing circuit which renders a synchronization between externally provided codes and internal codes.
2. Description of the Related Art
FIG. 1 shows a block configuration of one exmaple of a GPS receiving apparatus in the related art.
The GPS receiving apparatus 1 shown in the figure includes a receiving antenna 3, a receiving unit 4, an information processing device 5 and a display device 5.
The receiving antenna 2 receives GPS signals from GPS satellites 2-1 through 2-n. The GPS signals are signals of 1575.42 MHz. The GPS signals received by the receiving antenna 2 are provided to the receiving unit 4.
The receiving unit 4 extracts C/A codes (pseudo-random codes) from the GPS signals, and outputs data according to time difference between different C/A codes. The data output from the receiving unit 4 is provided to the information processing device 5.
The information processing device 5, according to the output data of the receiving unit 4, obtains information of latitude, longitude, altitude, time and so forth. The information processing device 5, accordintg to the thus-obtained information, drives the display device 6. The display device 6 displays the information of latitude, longitude, altitude, time and so forth obtained by the information processing device 4.
The receiving unit 4 will now be described.
FIG. 2 shows a block configuration of the receiving unit 4 shown in FIG. 1.
The receiving unit 4 includes a radio-frequency circuit 11, a receiving circuit 12, a CPU 13 and a RAM 14.
A received signal is provided to the radio-frequency circuit 11 from the antenna 3. The radio-frequency circuit 11 renders frequency conversion on the thus-provided received signal into a signal in a predetermined frequency band.
FIG. 3 shows a block configuration of the radio-frequency circuit 11.
The radio-frequency circuit 11 includes frequency converting parts 21 and 22, and an oscillating circuit 23. An oscillation signal of 18.414 MHz is provided to the oscillating circuit 23 from the receiving circuit 12. The oscillating circuit 23 includes a PLL (Phase Locked Loop) circuit, generates an oscillation signal of 1555.983 MHz from the thus-provided oscillation signal of 18.414 MHz, and provides the thus-generated signal to the frequency converting part 21.
The received signal having a carrier frequency of 1575.42 MHz is provided to the frequency converting circuit 21 from the antenna 3, and also, the oscillation signal of 1555.983 MHz is provided to the frequency converting circuit 21 from the oscillating circuit 23. The frequency converting part 21 multiplies the received signal with the oscillation signal of 1555.983 MHz, and converts the carrier frequency of the received signal into 19.437 MHz.
The received signal having thus undergone the frequency conversion by the frequency converting circuit 21 is provided to the frequency converting circuit 22. The oscillation signal of 18.414 MHz is provided to the frequency converting circuit 22 from the receiving circuit 12. The frequency converting circuit 22 multiplies the received signal from the frequency converting circuit 21 with the oscillation signal from the receiving circuit 12, and converts the received signal into a signal having a carrier frequency of 1.023 MHz. The signal obtained through the conversion by the frequency converting circuit 22 is provided to the receiving circuit 12.
The receiving circuit 12 extracts a satellite code according to the signal provided from the radio-frequency circuit 11.
FIG. 4 shows a block configuration of the receiving circuit 12.
The receiving circuit 12 includes a C/A-code generating circuit 31, multipliers 32 through 37, an oscillating circuit 38, a first detecting circuit 39, a second detecting circuit 40, a third detecting circuit 41 and a fourth detecting circuit 42.
The signal from the radio-frequency circuit 11 is provided to the multipliers 32 and 33. The multipliers 32 and 33 are connected to the oscillating circuit 38. The oscillating circuit 38 provides an oscillation signal accordintg to a carrier frequency of an I-signal to the multiplier 32, and provides an oscillation signal accordintg to a carrier-frequency of a Q-signal to the multiplier 33. The phase of the oscillating circuit 38 is controlled by a control signal from the CPU 13.
The C/A-code generating circuit 31 generates 3 types of C/A codes in timing according to the control signal from the CPU 13. The three types of C/A codes are a 0-chip delayed C/A code without delay, a −½-chip delayed C/A code having a delay of −½ chip from the 0-chip delayed C/A code, and a +½-chip delayed C/A code having a delay of +½ chip from the 0-chip delayed C/A code. The term ‘chip’ is a special term in the GPS technical field, and means a unit of a signal when the signal is divided in time axis.
The multiplier 32 multiplies the signal from the radio-frequency circuit 11 with the occultation signal from the oscillating circuit 38, and extracts the I-signal. The multiplier 33 multiplies the signal from the radio-frequency circuit 11 with the occultation signal from the oscillating circuit 38, and extracts the Q-signal.
The I-signal extracted by the multiplier 32 is provided to the multipliers 34 through 36. The I-signal is provided to the multiplier 34 from the multiplier 32, and, also, the −½-chip delayed C/A code is provided to the multiplier 34 from the C/A-code generating circuit 31. The multiplier 34 multiples the I-signal with the −½-chip delayed C/A code.
The I-signal is provided to the multiplier 35 from the multiplier 32, and, also, the 0-chip delayed C/A code is provided to the multiplier 35 from the C/A-code generating circuit 31. The multiplier 35 multiples the I-signal with the 0-chip delayed C/A code.
The I-signal is provided to the multiplier 36 from the multiplier 32, and, also, the +½-chip delayed C/A code is provided to the multiplier 36 from the C/A-code generating circuit 31. The multiplier 36 multiples the I-signal with the +½-chip delayed C/A code.
The Q-signal is provided to the multiplier 37 from the multiplier 33, and, also, the 0-chip delayed C/A code is provided to the multiplier 37 from the C/A-code generating circuit 31. The multiplier 37 multiples the Q-signal with the 0-chip delayed C/A code.
The multiplication result of the multiplier 34 is provided to the first detecting circuit 39. The multiplication result of the multiplier 35 is provided to the second detecting circuit 40. The multiplication result of the multiplier 36 is provided to the third detecting circuit 41. The multiplication result of the multiplier 37 is provided to the fourth detecting circuit 42.
The first detecting circuit 39 counts, from the multiplication result of the multiplier 34, chips in disagreement between the −½-chip delayed C/A code and I-signal, and, outputs the thus-obtained count value C1. The second detecting circuit 40 counts, from the multiplication result of the multiplier 35, chips in disagreement between the 0-chip delayed C/A code and I-signal, and, outputs the thus-obtained count value C2. The third detecting circuit 41 counts, from the multiplication result of the multiplier 36, chips in disagreement between the +½-chip delayed C/A code and I-signal, and, outputs the thus-obtained count value C3. The fourth detecting circuit 42 counts, from the multiplication result of the multiplier 37, chips in disagreement between the 0-chip delayed C/A code and Q-signal, and, outputs the thus-obtained count value C4.
The count values C1, C2, C3 and C4 output from the first through fourth detecting circuits 39 through 42 are provided to the CPU 13.
The CPU 13 obtains correlation values b1 through b4 from the count values C1 through C4. The correlation value b1 is a correlation value between the I-signal and −½-chip delayed C/A code. The correlation value b2 is a correlation value between the I-signal and 0-chip delayed C/A code. The correlation value b3 is a correlation value between the I-signal and +½-chip delayed C/A code. The correlation value b4 is a correlation value between the Q-signal and 0-chip delayed C/A code.
The correlation values b1 through b4 are obtained by the following formulas assuming that the count value in a case where there is no correlation is ‘a’:b1=C1−a  (1)b2=C2−a  (2)b3=C3−a  (3)b4=C4−a  (4)
The CPU 13 obtains a correlation d0 between the I-signal and Q-signal, and the internally generated code from the correlation value b2 and correlation b4 by the following formula (5):d0=(b22+b42)  (5)
The CPU 13 compares the correlation d0 with a threshold. When the correlation d0 is smaller than the threshold (this means that the correlation between the received signal and internally generated code is small) and also the phase shift amount has reached 1023 chips (a condition in which it is determined that the frequency difference is so large that the predetermined correlation cannot be obtained therebetween although the phase is shifted through the maximum range), the CPU 13 provides a frequency control signal to the oscillating circuit 38. The oscillating circuit 38 controls the frequency of the oscillation signal provided to the multipliers 32 and 33 accordintg to the frequency control signal from the CPU 13. The CPU 13 repeats the above-mentioned operation until the correlation d0 exceeds the threshold (the phase difference therebetween becomes sufficiently small).
When the correlation d0 exceeds the threshold, the CPU 13 performs a lock operation. The lock operation is such that CPU 13 controls the oscillating circuit 38 according to the correlation d0, and monitors the correlation between the I-signal and Q-signal, and the internally generated code. The correlation d0 between the I-signal and Q-signal, and the internally generated code is provided to the information processing device 5.
The information processing device 5 renders a synchronization with the signal from the satellite by using the correlation d0 between the I-signal and Q-signal, and the internally generated code provided from the CPU 13, obtains information therefrom, and extracts position information therefrom. A map is displayed by the display device 6, and, a position according to the thus-extracted position information is displayed on the thus-displayed map. Further, the CPU 13 performs the lock operation according to the correlation value b1 and correlation value b3. With regard to the principle and so forth for obtaining position information and so forth from the GPS signal (signal from satellites), they are well known in the GPS technical field, and detailed description thereof is omitted.
However, in such a search method in the related art, only the correlation between one pair of 0-chip delay of I-signal and 0-chip delay of Q-signal is utilized. Accordingly, the C/A-code can be shifted only by one chip every time in the search operation.
Thereby, a considerable time is required for the search.